An SRAM (Static Random Access Memory) is a semiconductor device provided with a transfer transistor to be selected by a word line, and two CMOS (Complementary Metal Oxide Semiconductor) inverters connected to a bit line through the transfer transistor. Each CMOS inverter includes an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor is formed in a P-type well region (P well) of a semiconductor substrate, whereas the P-type MOS transistor is formed in an N-type well region (N well) of the semiconductor substrate.
In each CMOS inverter, the semiconductor substrate and the transistors are electrically isolated from each other by the well regions. A parasitic thyristor having a pnpn structure is therefore formed between a power supply and a GND terminal in the semiconductor substrate. If radioactive rays are radiated to the SRAM, the parasitic thyristor goes into an electroconductive state, thus in some cases causing latch-up (Single Event Latch-up (SEL)) in which a current continues to flow between the power supply and the GND terminal. Accordingly, a P well high in impurity concentration is formed underneath a region of the semiconductor substrate where the SRAM is formed (hereinafter referred to as the SRAM region) to reduce the resistance of the semiconductor substrate, thereby reducing the occurrence of problems, such as latch-up.
Triple well structures in which a P well is surrounded by N wells are formed in a high-withstand voltage region and an I/O (Input Output) region of the semiconductor substrate. The P well may be formed underneath the SRAM region in some cases in the semiconductor substrate including the SRAM and the triple well structures.
[Patent document 1] Japanese Laid-open Patent Publication No. 05-267606
[Patent document 2] Japanese Laid-open Patent Publication No. 10-135351